The steps of fabricating multi-layer ceramic substrates for integrated circuit package assemblies are well-known. Generally, a paste or slurry is prepared combining ceramic particulates (e.g. alumina), a binder and solvent therefor. The paste is cast or doctor bladed into sheets which are then dried and sized. The dried sheets are subsequently punched to form via holes; and screened to provide metallurgy to fill the via holes. The sheets are then stacked, laminated and sintered. The sintered substrates can be employed for mounting semiconductor devices which are electrically connected to the internal circuitry of the substrate.
Electrical connection from an external power source to the internal circuitry of the substrate is made through input/output, I/O, pins mounted on the bottom of the substrate. Electrical connection on the top of the substrate must be made to the integrated circuit devices and among engineering change, EC, pads. it is necessary, therefore, to provide a relatively complex metallurgy to the substrate.
On the top surface of the substrate, there may be dozens of EC pads along with I/O pad patterns designated for mounting, perhaps, nine integrated circuit "chips". The chip mounting is generally done using a "flip-chip" orientation whereby the chips are mounted to the I/O pads on the substrate surface using a solder reflow or similar standard process. In order to achieve a good bond for the lead-tin solder, the chip mounting, I/O pad is frequently prepared with a thin coat of gold on a thin coat of nickel deposited over the molybdenum via metallurgy. U.S. patent application Ser. No. 359,469 of A. H. Kumar et al, now U.S. Pat. No. 4,493,856, assigned to assignee of the present invention, discusses a two-material metallization process applied to both the I/O and EC pads. Those teachings are herein incorporated by reference. As discussed therein, nickel has excellent adhesion to molybdenum and the subsequent thin flash layer of gold prevents oxidation of the nickel. In addition, the very thin coating of gold on the I/O pads allows for a good solder bond for chip mounting. A heavy concentration of gold on the I/O pads, however, could contaminate the lead-tin solder and result in poor adhesion. The nickel and gold-treated EC pads, on the other hand, require additional heavy plating with gold to allow for frequent and repeated changes in the wire bonding to the pads thereby accommodating testing, engineering changes and defect compensation.
The need to plate the conductive pad patterns, EC and I/O, differently is discussed in patent application Ser. No. 560,661 of Christensen, et al, now U.S. Pat. No. 4,526,859, assigned to the assignee of the present invention and herein incorporated by reference. There, the use of photoresists as masking layers is discussed for use in obtaining a heavy metal, for example gold, coating on either only the EC pads or only the I/O pads. The use of resists as masks is well-known, as evidenced by the teachings in Japanese application No. 50-124930, publication No. 52-48992, Apr. 19, 1977 and in U.S. Pat. No. 3,957,552 of Ahn, et al. As in Christensen, et al, the references teach the application of a resist, selective exposure of the resist using an appropriate mask and development of the exposed resist forming a pattern and revealing the underlying surface intended to be metallized. Metallization of the entire surface follows whereby the metal layer is deposited on the unexposed resist and on the patterned underlying surface. Removal by float-away or etching techniques of the remaining resist with overlying metal results in a clean, metal-patterned surface.
Similarly, metal masks can be used by placing them in registration with the substrate and, essentially, screening through the mask. It is frequently difficult however to achieve registration of a pre-formed metal mask with a substrate which has undergone uneven shrinkage during sintering.
The method of depositing the metal may be one of many well-known techniques. The Christensen, et al reference utilizes dry deposition processes such as magnetron sputtering or ion plating, in gross, with photoresists in place. Indiscriminate deposition of metal over the entire surface may also be obtained by painting the metal (See: U.S. Pat. No. 3,741,735, Buttle), dipping the article in molten metal (See: U.S. Pat. No. 2,788,289 to Double), sputtering, evaporation techniques or vapor deposition (all well-known methods cited in U.S. Pat. No. 4,293,587 of Trueblood). In all of these processes, a subsequent resist patterning and metal etching step is required to remove excess metal from the substrate. Electroplating, such as is seen in IBM Technical Disclosure Bulletin, Vol. 22 No. 4, September ', 79, page 1439 by Kowalczyk, is a metal deposition method which can insure specific application of overlay metal to the intended metal pattern by providing a conductive path to only those pads to be plated. Another known method of deposition requiring no masking step is the maskless cladding process described in U.S. Pat. No. 4,442,137 to Kumar. Therein, a blanket metal coating is deposited, by sputtering, vapor deposition or other known process, and subsequently heated to a temperature sufficient to cause the overlying, e.g. gold, coat to diffuse with the underlying metallurgy. At the same time as the metal-to-metal diffusion is occurring, the varying shrinkage rates of the substrate material and the overlying metal produce stresses sufficient to cause the metal deposited on the substrate to flake or spall and consequently be readily removable in a follow-up mechanical cleaning step, such as ultrasonic removal of the residue.
The deposition and diffusion, however, is nonselective and therefore causes the heavy overlying metal to diffuse and adhere to all of the metal interconnection pads, EC and I/O alike. As noted above, it is desirable to have a thick gold coating on the EC pads but not on the I/O , chip mounting, pads.
It is therefore an object of the present invention to provide a method for depositing metal onto a selected portion of a metallurgical pattern.
It is another object of the invention to provide an isolation barrier against metal deposition to a selected portion of a metallurgical pattern.
It is a further object of the invention to provide an isolation barrier for use in a maskless cladding operation.
It is still another object to provide an isolation barrier having the thermal integrity to withstand metal deposition temperatures and the mechanical and thermal integrity to support a metal overlay film during subsequent diffusion steps.
It is a final object to provide a substrate isolation barrier having the thermal and mechanical integrity to withstand necessary processing and being readily removable leaving no residue on the substrate.